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Frame Status FIFO Circuitry
SCC Status Reg Residue Bits (3) Overrun, CRC Error Reset on Flag Detect Byte Counter Increment on Byte Detection Enable Count in SDLC End of Frame Signal Status Read Comp Tail Pointer 4-Bit Counter Head Pointer 4-Bit Counter 4-Bit Comparator Over 5 Bits EOF = 1 6 Bits 8 Bits Equal
RR1
5 Bits FIFO Array 10 Deep by 19 Bits Wide
14 Bits
6-Bit MUX
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2 Bits
6 Bits RR1
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Bits 5-0
RR6
FIFO Enable
Interface to SCC
RR7 D5-D0 + RR6 D7-D0 Byte Counter Contains 14 bits for a 16 KByte maximum count RR7 D6 FIFO Data available status bit Status Bit set to 1 When reading from FIFO RR7 D7 FIFO Overflow Status Bit MSB pf RR(7) is set on Status FIFO overflow
WR(15) Bit 2 Set Enables Status FIFO
In SDLC Mode the following definitions apply - All Sent bypasses MUX and equals contents of SCC Status Register - Parity Bits bypasses MUX and does the same - EOF is set to 1 whenever reading from the FIFO
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Internal Byte Strobe Increments Counter Don't Load Counter On 1st Flag Reset Byte Counter Here Reset Byte Counter Load Counter Into FIFO and Increment PTR
Internal Byte Strobe Increments Counter Reset Byte Counter Reset Byte Counter Load Counter Into FIFO and Increment PTR
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Write Register 0 (non-multiplexed bus mode) D7 D6 D5 D4 D3 D2 D1 D0
Write Register 1 D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 1
0 1 0 1
000 001 010 011 100 101 110 111 Null Code Reset Rx CRC Checker Reset Tx CRC Generator Reset Tx Underrun/EOM Latch
0 0 0 Register 0 0 0 1 Register 1 0 1 0 Register 2 0 1 1 Register 3 1 0 0 Register 4 1 0 1 Register 5 1 1 0 Register 6 1 1 1 Register 7 0 0 0 Register 8 0 0 1 Register 9 0 1 0 Register 10 0 1 1 Register 11 * 1 0 0 Register 12 1 0 1 Register 13 1 1 0 Register 14 1 1 Register 15 Null Code Point High Reset Ext/Status Interrupts Send Abort (SDLC) Enable Int on Next Rx Character Reset Tx Int Pending Error Reset Reset Highest IUS
Ext Int Enable Tx Int Enable Parity is Special Condition 0 0 1 1 0 1 0 1 Rx Int Disable Rx Int on First Character or Special Condition Int on all Rx Characters or Special Condition Rx Int on Special Condition Only WAIT/DMA Request on Receive /Transmit WAIT/DMA Request Function WAIT/DMA Request Write Register 2 D7 D6 D5 D4 D3 D2 D1 D0 V0 V1 V2 V3 V4 V5 V6 Interrupt Vector
* With Point High Command
Write Register 0 (multiplexed bus mode) D7 D6 D5 D4 D3 D2 D1 D0 Write Register 3 0 0 1 1 0 1 0 1 Null Code Null Code Select Shift Left Mode Select Shift Right Mode 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Null Code Null Code Reset Ext/Status Interrupts Send Abort Enable Int on Next Rx Character Reset Tx Int Pending Error Reset Reset Highest IUS D7 D6 D5 D4 D3 D2 D1 D0 *
V7
Rx Enable Sync Character Load Inhibit Address Search Mode (SDLC) Rx CRC Enable Enter Hunt Mode Auto Enables 0 0 1 1 0 1 0 1 Rx 5 Bits/Character Rx 7 Bits/Character Rx 6 Bits/Character Rx 8 Bits/Character
Null Code Reset Rx CRC Checker Reset Tx CRC Checker Reset Tx Underrun/EOM Latch
* B Channel Only
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Write Register 4 D7 D6 D5 D4 D3 D2 D1 D0
Write Register 5 D7 D6 D5 D4 D3 D2 D1 D0
Parity Enable Parity EVEN/ODD 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Sync Modes Enable 1 Stop Bit/Character 1 1/2 Stop Bits/Character 2 Stop Bits/Character 0 0 1 1 0 1 0 1 Tx 5 Bits (or Less)/Character Tx 7 Bits/Character Tx 6 Bits/Character Tx 8 Bits/Character
Tx CRC Enable RTS SDLC/CRC-16 Tx Enable Send Break
8-Bit Sync Character 16-Bit Sync Character SDLC Mode (01111110 Flag) External Sync Mode
DTR 0 0 1 1 0 X1 Clock Mode 1 X16 Clock Mode 0 X32 Clock Mode 1 X64 Clock Mode
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Write Register 6 D7 D6 D5 D4 D3 D2 D1 D0
Sync7 Sync1 Sync7 Sync3 ADR7 ADR7
Sync6 Sync0 Sync6 Sync2 ADR6 ADR6
Sync5 Sync5 Sync5 Sync1 ADR5 ADR5
Sync4 Sync4 Sync4 Sync0 ADR4 ADR4
Sync3 Sync3 Sync3 1 ADR3 x
Sync2 Sync2 Sync2 1 ADR2 x
Sync1 Sync1 Sync1 1 ADR1 x
Sync0 Sync0 Sync0 1 ADR0 x
Monosync, 8 Bits Monosync, 6 Bits Bisync, 16 Bits Bisync, 12 Bits SDLC SDLC (Address Range)
Write Register 7 D7 D6 D5 D4 D3 D2 D1 D0
Sync7 Sync6 Sync5 Sync4 Sync15 Sync14 Sync11 Sync10 1 0
Sync5 Sync3 Sync13 Sync9 1
Sync4 Sync2 Sync12 Sync8 1
Sync3 Sync1 Sync11 Sync7 1
Sync2 Sync1 Sync0 x Sync0 x Sync10 Sync9 Sync8 Sync6 Sync5 Sync4 1 1 0
Monosync, 8 Bits Monosync, 6 Bits Bisync, 16 Bits Bisync, 12 Bits SDLC
WR 7' Prime (85C30 only) D7 D6 D5 D4 D3 D2 D1 D0
Auto Tx Flag Auto EOM Reset Auto RTS Deactivation Force TxD High DTR/REQ Fast Mode Complete CRC Reception Extended Read Enable Reserved (Program as 0)
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Write Register 9 D7 D6 D5 D4 D3 D2 D1 D0
Write Register 9 D7 D6 D5 D4 D3 D2 D1 D0
VIS NV DLC MIE Status High/Status Low Software INTACK Enable 0 0 1 1 0 1 0 1 No Reset Channel Reset B Channel Reset A Force Hardware Reset Write Register 13 D7 D6 D5 D4 D3 D2 D1 D0 Write Register 9 D7 D6 D5 D4 D3 D2 D1 D0
TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 Lower Byte of Time Constant
TC8 TC9 6-Bit/8-Bit Sync Loop Mode Abort/Flag on Underrun Mark/Flag Idle Go Active on Poll TC10 TC11 TC12 TC13 TC14 TC15 Write Register 14 D7 D6 D5 D4 D3 D2 D1 D0 CRC Preset I/O BR Generator Enable Upper Byte of Time Constant
0 0 1 1
0 NRZ 1 NRZI 0 FM1 (Transition = 1) 1 FM1 (Transition = 0)
Write Register 11 D7 D6 D5 D4 D3 D2 D1 D0
BR Generator Source DTR/Request Function Auto Echo 0 0 1 1 0 1 0 1 TRxC Out = Xtal Output TRxC Out = Transmit Clock TRxC Out = BR Generator Output TRxC Out = DPLL Output TRxC O/I Local Loopback 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Null Command Enter Search Mode Reset Missing Clock Disable DPLL Set Source = BR Generator Set Source = RTxC Set FM Mode Set NRZI Mode
0 0 1 1 0 0 1 1
0 Transmit Clock = RTxC Pin 1 Transmit Clock = TRxC Pin 0 Transmit Clock = BR Generator Output 1 Transmit Clock = DPLL Output
Write Register 15 0 Receive Clock = RTxC Pin 1 Receive Clock = TRxC Pin 0 Receive Clock = BR Generator Output 1 Receive Clock = DPLL Output RTxC Xtal/No Xtal D7 D6 D5 D4 D3 D2 D1 D0
0 Zero Count IE SDLC FIFO Enable DCD IE Sync/Hunt IE CTS IE Tx Underrun/EOM IE Break/Abort IE
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Read Register 0 D7 D6 D5 D4 D3 D2 D1 D0
Read Register 3 D7 D6 D5 D4 D3 D2 D1 D0
Rx Character Available Zero Count Tx Buffer Empty DCD Sync/Hunt CTS Tx Underrun/EOM Break/Abort Read Register 1 D7 D6 D5 D4 D3 D2 D1 D0 * Always 0 in B Channel Read Register 10 D7 D6 D5 D4 D3 D2 D1 D0 All Sent Residue Code 2 Residue Code 1 Residue Code 0 Parity Error Rx Overrun Error CRC/Framing Error End of Frame (SDLC)
Channel B Ext/Status IP Channel B Tx IP Channel B Rx IP Channel A Ext/Status IP Channel A Tx IP Channel A Rx IP 0 0 *
0 On Loop 0 0 Loop Sending 0 Two Clocks Missing One Clocks Missing
Read Register 2 D7 D6 D5 D4 D3 D2 D1 D0 Read Register 12 D7 D6 D5 D4 D3 D2 D1 D0 V0 V1 V2 V3 V4 V5 V6 V7 * Modified in B Channel Interrupt Vector * TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 Lower Byte of Time Constant
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Read Register 13 D7 D6 D5 D4 D3 D2 D1 D0
Read Register 15 D7 D6 D5 D4 D3 D2 D1 D0
TC8 TC9 TC10 TC11 TC12 TC13 TC14 TC15 Upper Byte of Time Constant
0 Zero Count IE 0 DCD IE Sync/Hunt IE CTS IE Tx Underrun/EOM IE Break/Abort IE
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